1. Field of the Invention
This invention relates generally to minicomputer systems and more particularly to storage hierarchies having high speed, low capacity storage devices and lower speed, high capacity storage devices coupled in common to a systems bus.
2. Description of the Prior Art
The storage hierarchy concept is based on the phenomena that individual stored programs under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the CPU interface, and in addition include various levels of increasing capacity slower storage, can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.
Prior art systems provide a relatively small size buffer or cache interposed between the main memory and the central processor unit (CPU) to improve systems throughput. The CPU requests information from cache. If the information is not in cache it is requested of main memory. In order for this system to work well, information in both cache and main memory at address locations identified by the same address bit configurations must be the same information. At the conclusion of the initialization process there must be a means of assuring that residual information left in cache from a previous operation does not adversely impact the system.
U.S. Pat. No. 3,840,862 issued to D. T. Ready entitled "Status Indicator Apparatus for Tag Directory in Associative Stores" and U.S. Pat. No. 3,845,474 issued to R. E. Lange, et al., entitled "Cache Store Clearing Operation for a Multiprocessor Mode" both describe the use of full/empty or validity bits to indicate valid from invalid information in cache.
In addition to eliminating the need for full/empty or validity bits with their associated circuitry, the invention described herein improves the test and diagnostic capabilities of the cache system.